85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate

Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 5cb4a13e085cb4fca91e1301ba0e98381fa8740a..fccc4f8f5891e85447afd35bf42cc3d9945d7ba4 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
 #define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
 #define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800    0x02000000
-#define CONFIG_SYS_DDR_MODE_1_800      0x00440862
+#define CONFIG_SYS_DDR_CLK_CTRL_800    0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_800      0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100